Application of 10Gbps XFP Transceiver in XFP Optical Module

In the optical fiber communication system, to achieve optical / electrical / optical conversion function of the optical transceiver module occupies a very important position. Although high-speed (40,100 Gbit / s) technology has become the focus of major operators, but 10Gbit / s technology is still the mainstream of the current communication system technology. The 10Gbit / s XFP optical module, which is hot-swappable and small in circuit area, is a mainstream product of 10Gbit / s optical module with its low price, small size and wide application environment.

XFP optical module transmitter, including optical transmission subsystem, CDR clock data recovery circuit, temperature control circuit and control circuit, using input equalizer, multi-rate CDR, EML (electroabsorption modulation laser) driver and APC integrated chip-driven laser To achieve electrical / optical conversion. The receiving end includes the optical receiving subsystem, the main chip and the control circuit. The APD (avalanche photodiode) is used to convert the detected optical signal into electrical signal and then output. Using single-chip control transceiver chip to achieve digital diagnostic functions.

Introduction to Si5040
Silocn Labs introduced the 10Gbps XFP transceiver Si5040, is the industry's first in the data transmission and reception path can provide signal jitter elimination function of the transceiver. The Si5040 is also the only transceiver capable of continuously supporting all telecom and data communication protocols between 9.9Gbps ​​and 11.4Gbps, as well as signal jitter cancellation capabilities, and supports multiple transmission rates such as OC-192 / STM-64, 10GbE, 10G Fiber Channel and FEC. Combined with the industry's smallest package of 5 x 5mm, and low power consumption, low jitter and other excellent performance makes it very suitable for space-constrained XFP module applications.

Si5040 is the use of Silicon Labs DSPLL patented technology to eliminate optical module transmission 10Gbps serial data stream due to network or line card system-level noise generated by the signal degradation and jitter phenomenon. This technique reduces the jitter of the transmit signal to the 2.5 mUI RMS in the transceiver path, eliminating the need for jitter cancellation circuitry inside the XFP module and on the optical line card. At the same time, the receiving path of the DSPLL can also receive data jitter amplitude to a minimum, to ensure that with the optical line card ASIC or FPGA chip connection does not produce errors.

The Si5040 XFP optical module provides the industry's most complete functionality. Including support for analog signal LOS monitoring, CID (with 0 or even 1) monitoring and proprietary digital eye opening measurement function of three different analog and digital signal quality monitoring functions. It also provides a series of tests and functions that make system-level testing and debugging simpler, such as line loopback testing, XFI loop testing, and receive and send bidirectional PRBS bit stream generation and checking functions. With the module control MCU through the bus to achieve the special register read and write to complete the XFP optical module to receive loss of alarm and TO-SA temperature, TEC (temperature control circuit) current, the transmitter bias current, modulation current, receive optical power and other diagnostic functions The
Si5040 application circuit

Si5040 application circuit shown in Figure 2 below. The peripheral circuit is divided into the following parts:
• Differential receive / transmit signal input and output signal channels, only 0.1uF DC blocking capacitor
• 1V8 single power supply
• Reference clock input
• 2-wire serial control bus, the chip supports I2C and SPI-Like two bus mode. The two bus modes are selected by the SPSEL pin, SPSEL low selects I2C mode, and vice versa selects SPI-Like mode. When I2C mode is selected, the SS pin is used to select the I2C address, SS is low. The I2C address is 7d '1000001, SS is floating or high. The I2C address is 7d' 1000000.

This shows that the circuit peripheral components less, very suitable for use in a compact XFP module, greatly simplifying the complexity of circuit design and improve system stability.

Si5040 reference clock input
The Si5040 can flexibly support three clock operation modes to enable XFP modules to accommodate both data communications and carrier-class applications.

1) No reference clock mode Referenceless Mode (Mode 0)
This mode applies only to no external reference clock, or the external reference clock jitter is higher than the clock recovered by the RX CDR. Power UP defaults to this mode.

2) Synchronous Reference Clock Mode Synchronous Reference Clock Mode (Mode 1)
This mode will provide the best clock jitter performance. The CMU in this mode provides a 64x REFCLK clock as the line card clock, which is equivalent to the "Optional Synchronous CMU Clock" mode defined in XFP MSA Rev. 4.0 Section 3.9.1. Since the Si5040 sends the CMU to debounce the reference clock, it does not require additional processing to meet the phase noise requirements required in the XFP synchronous clock mode.

3) Asynchronous reference clock mode Asynchronous Reference Clock Mode (Mode 2)
This mode is used when the external asynchronous reference clock jitter is below the clock recovered by the RX CDR. The external reference clock is used as the TX CMU reference clock source. The TX frequency is locked on the TX input data, but thanks to the low jitter reference clock, the TX clock reduces jitter. Data path on the FIFO application, making the clock system to adapt to different serial data and CMU line card clock jitter difference.

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